1. Field of the Invention
The present invention relates to processor data buses, and more particularly to a target readiness protocol apparatus and method that enable a microprocessor or like device to perform contiguous writes to memory.
2. Description of the Related Art
The bus interface of most microprocessors is substantially similar with minor variation. Memory addresses for transactions are provided over a bidirectional address bus referred to herein as ADDR. A bidirectional address strobe signal, referred to herein as ADS, indicates validity of the addresses on the ADDR bus. Data is transferred over a bidirectional data bus referred to herein as DATA. In some present day microprocessor architectures, eight bytes are transferred at a time, which quantity (8 bytes) is known as a “beat.” In a present day quad-pumped data bus, such as is provided in the well-known PENTIUM® 4 microprocessor, four beats are transferred during each cycle of a bus clock signal, referred to herein as BCLK, and up to eight beats (64 bytes) can be transferred during a single transaction to accommodate transfer of an entire 64-byte cache line to or from memory. A bidirectional data bus busy signal, referred to herein as DBSY, is asserted by the entity that is providing the data (i.e., microprocessor or bus agent) during all but the final clock cycle that data is transferred over the DATA bus. The providing entity asserts DBSY to indicate that it is taking ownership of the DATA bus. A data ready signal, referred to herein as DRDY, is asserted by either the microprocessor or bus agent during all clock cycles that data is transferred over the DATA bus. The device that is providing the data asserts DRDY. A target ready signal, referred to herein as TRDY, is asserted only by the target device (e.g., the chipset) from which a write transaction has been requested. Assertion of TRDY indicates that the target agent is ready to provide the data for the write transaction. In addition, a response bus, referred to herein as RS, is asserted by the target agent to indicate the type of transaction response (e.g., no data, normal data, implicit writeback) that is being completed over the DATA bus.
Some processors multiplex addresses and data over the same signal group and thus provide control signals to indicate whether data or addresses are present. Other microprocessors utilize different address or data bus widths or control signals alternatively named. It is important to note that substantially all processors provide signals for communication with bus agents to indicate that the data bus is ready, that it is busy, and to receive indication from the bus agents that the agent is ready to receive the data corresponding to a write transaction.
Because the data associated with combined writes (e.g., write combines, non-temporal stores) is typically large, it is disadvantageous to not fully utilize the bandwidth of a data bus, whether that bus is quad pumped or otherwise. Since data buses typically operate at clock speeds many times slower than that of microprocessor core clocks, it is crucial to execute combined writes to memory with optimum efficiency. The inefficient utilization of bus bandwidth in a present day microprocessor is a consequence of the rules for deasserting the TRDY signal, referred to herein as the Target Readiness Protocol (TRP) rules. More particularly, because TRDY cannot be deasserted until the cycle following the cycle where it is confirmed that DBSY is deasserted according to the TRP rules, combined writes in a quad-pumped data bus can only employ a percentage of the bus bandwidth. This “handshake” of DBSY and TRDY (or analogous signals) is a de facto industry standard and serves to limit the flow of data to memory. Because of the rules associated with TRDY, it is impossible to saturate a present day data bus with write data.